Until the early 1970s, electronic circuits were analyzed and designed almost exclusively by hand. Since that time, the ever increasing demand for more complex integrated circuits (ICs) has made computer aided design (CAD) and computer aided engineering (CAE) tools practically indispensable in the design of ICs, as such tools enable the rapid synthesis, optimization and analysis of an IC design, using parameters as specified by the designer. CAD and CAE tools can also manage masses of data that would otherwise overwhelm the designer, while computer-based layout design systems are useful in preparing and modifying the geometric patterns, or "layouts," required for IC masks.
A large amount of random logic undergoes automated synthesis during the design of an IC. In general, automated synthesis allows a user to describe, in a high level language, for example, Verilog or VHDL, what functions the IC is to perform, at which point a CAE tool will turn the description into the actual gates and transistors and interconnections thereof comprising the IC. One CAE tool commonly used for such automated synthesis and optimization is SYNOPSYS, available from Synopsys, Inc., of Mountain View, Calif. In operation, SYNOPSYS makes use of a cell library comprising a large set of simple logic cells, such as NAND, NOR, AND and OR gates, as well as flip flops and latches, of varying sizes and numbers of inputs. A large cell library will result in a more efficient and accurate synthesis, as it gives SYNOPSYS a greater number of options in synthesizing a given circuit.
The two main goals to be achieved with automated synthesis are maximizing the overall performance, or speed, of the IC, while minimizing the overall area of, and therefore the expense of producing and power consumed by, the IC. More often than not, these two goals will be at odds with one another, as a large cell will drive a large load faster, but consume more power, than a smaller cell can drive the same load. Accordingly, for each cell in the cell library, SYNOPSYS must be given a good idea of the propagation delay, that is, the speed, of the cell. It is generally accepted that the two parameters that have the greatest effect on the propagation delay of a cell are the size of the load being driven by the cell, designated C.sub.load, and the input transition time, designated S.sub.in, of the cell. Accordingly, each cell in the library must be "characterized" with respect to timing characteristics thereof such that, for a given input transition time and load value, SYNOPSYS is able to determine the resulting transition delay of the cell.
In this regard, SYNOPSYS supports two timing models, which are a three term linear model of the form: EQU t.sub.d =a.sub.0 +a.sub.1 S.sub.in +a.sub.2 C.sub.load
where t.sub.d is the propagation delay of the cell, S.sub.in is the input transition time of the cell, and C.sub.load is the load being driven by the cell, and a lookup table model of the form: EQU t.sub.d =cell.sub.-- delay+output.sub.-- tran
where values for cell.sub.-- delay (cell delay) and output.sub.-- tran (output transition time) for varying values of S.sub.in and C.sub.load are stored in lookup tables. In short, characterizing a cell involves computing SYNOPSYS propagation delay parameters for the cell for each of the models. Characterizing a library of 1500 cells would typically take about 3 man-months, that is, it would take one person three months to characterize an entire library. Clearly, automating this task would be a great advantage in terms of conservation of engineering time.
Therefore, what is needed is a utility for automatically computing timing characteristics for each cell in a standard cell library for use by an automated synthesis and optimization tool, such as SYNOPSYS.